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Nic30 / hwt
80%
master: 84%

Build:
Build:
LAST BUILD BRANCH: HEAD
DEFAULT BRANCH: master
Repo Added 07 Jun 2017 12:41PM UTC
Files 191
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LAST BUILD ON BRANCH verilogSerializer
branch: verilogSerializer
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  • verilogSerializer
  • HEAD
  • HStream_integration
  • master
  • rmSimpy
  • sharedProcesses
  • systemCSim
  • transactional_memories
  • v1.7
  • v1.8
  • v1.9
  • v2.1
  • v2.2
  • v2.3
  • v2.4
  • v2.5
  • v2.6
  • v2.7
  • v2.8
  • v2.9
  • v3.0
  • v3.1
  • v3.2
  • v3.3
  • v3.4
  • v3.5
  • v3.6
  • v3.7
  • verilator_sim

pending completion
252

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travis-ci

Nic30
VerilogSerializer IfContainer with event operator

6557 of 8203 relevant lines covered (79.93%)

0.8 hits per line

Relevant lines Covered
Build:
Build:
8203 RELEVANT LINES 6557 COVERED LINES
0.8 HITS PER LINE
Source Files on verilogSerializer
Detailed source file information is not available for this build.

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
252 verilogSerializer VerilogSerializer IfContainer with event operator push 10 Jun 2017 04:47PM UTC Nic30 travis-ci pending completion  
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