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Nic30 / hwt
86%
master: 84%

Build:
Build:
LAST BUILD BRANCH: HEAD
DEFAULT BRANCH: master
Repo Added 07 Jun 2017 12:41PM UTC
Files 190
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LAST BUILD ON BRANCH verilator_sim
branch: verilator_sim
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  • verilator_sim
  • HEAD
  • HStream_integration
  • master
  • rmSimpy
  • sharedProcesses
  • systemCSim
  • transactional_memories
  • v1.7
  • v1.8
  • v1.9
  • v2.1
  • v2.2
  • v2.3
  • v2.4
  • v2.5
  • v2.6
  • v2.7
  • v2.8
  • v2.9
  • v3.0
  • v3.1
  • v3.2
  • v3.3
  • v3.4
  • v3.5
  • v3.6
  • v3.7
  • verilogSerializer

pending completion
940

push

travis-ci

Nic30
doc

2771 of 3523 branches covered (78.65%)

Branch coverage included in aggregate %.

8236 of 9221 relevant lines covered (89.32%)

0.89 hits per line

Relevant lines Covered
Build:
Build:
9221 RELEVANT LINES 8236 COVERED LINES
0.89 HITS PER LINE
Source Files on verilator_sim
  • List 0
  • Changed 0
  • Source Changed 0
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
940 verilator_sim doc push 07 Nov 2019 04:07PM UTC Nic30 travis-ci pending completion  
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  • Repo on GitHub
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