nickg / nvc / 37856545577
92%
master: 92%

LAST BUILD BRANCH: vlog-timing-checks
DEFAULT BRANCH: master
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Jobs 1
Files 103
Run time 1min
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coverage: 92.44%. Remained the same
37856545577

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nickg 
Fix connecting VHDL signals to SV input logic ports

81623 of 88298 relevant lines covered (92.44%)

674108.61 hits per line

Jobs
ID Job ID Ran Files Coverage
1 37856545577.1 103
92.44
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Source Files on build 37856545577