nickg / nvc / 30523462561
92%

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Jobs 1
Files 103
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coverage: 92.164% (+0.001%) from 92.163%
30523462561

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nickg 
Allow unpacked dimensions in System Verilog port declarations

Fixes #1625

9 of 9 new or added lines in 2 files covered. (100.0%)

80218 of 87038 relevant lines covered (92.16%)

658467.69 hits per line

Jobs
ID Job ID Ran Files Coverage
1 30523462561.1 103
92.16
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Source Files on build 30523462561