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nickg / nvc / 30522106131
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 30 Jul 2026 07:26AM UTC
Jobs 1
Files 103
Run time 1min
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30 Jul 2026 07:11AM UTC coverage: 92.163%. Remained the same
30522106131

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nickg
Allow unpacked dimensions in System Verilog port declarations

9 of 9 new or added lines in 2 files covered. (100.0%)

80217 of 87038 relevant lines covered (92.16%)

637760.75 hits per line

Jobs
ID Job ID Ran Files Coverage
1 30522106131.1 30 Jul 2026 07:25AM UTC 103
92.16
GitHub Action Run
Source Files on build 30522106131
  • Tree
  • List 103
  • Changed 3
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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