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arnavsacheti / PeakRDL-BusDecoder / 28897292023
92%

Build:
DEFAULT BRANCH: main
Ran 07 Jul 2026 08:45PM UTC
Jobs 1
Files 36
Run time 1min
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07 Jul 2026 08:42PM UTC coverage: 92.4% (+0.08%) from 92.322%
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fix: correct decode boundaries below rolled array ancestors (#56, #57) (#71)

A decode boundary that sits below one or more rolled array ancestors was
generating broken SystemVerilog. Both reported issues are symptoms of the
same hole -- generators tracked only a node's own array dimensions and
numbered loop variables inconsistently across stages.

Loop-variable numbering (#56): make BusDecoderListener the single source of
truth. The open-dim stride stack now holds one entry per open loop dimension
in a contiguous outermost-first order (design_scanner stores strides
outermost-first; the listener extends rather than append/appendleft). A new
loop_base_index() hands every generator (decode/fanin/fanout/intermediate)
the first i{k}/gi{k} for a node's own dims, so the numbers line up with the
stride order used by cpuif_addr_predicate and with get_indexed_path from the
top node. This fixes shadowed inner loops, undeclared i1 references, and the
drifting i2-vs-i1 mismatch in the decoder.

Ports/intermediates under array ancestors (#56/#57): a boundary below rolled
arrays is an interface array sized by ALL open dims (ancestors' + own).
DesignState.open_array_dims() plus BaseCpuif.is_master_array/master_array_dims
plumb this through port declarations (SVInterface + FlatInterface), the
signal() index expressions (now indexed from the top node so ancestor
brackets are included), the fanin_wr/rd SV-array overrides, and a rewritten
FaninIntermediateGenerator that declares/assigns per boundary node (not per
rolled node) sized by every open dim. Fixes scalar ports for arrayed masters,
mis-sized fanin intermediates, and the duplicate bar_fanin_ready[3]/[5]
declarations from #57.

Select-struct typedef collisions (#57): two internal nodes with the same
instance name under different parents (group_a.bar / group_b.bar) emitted
duplicate cpuif_sel_bar_t typedefs. DesignState.struct_type_name() qualifies
colliding names by top-relative path, mirroring master_port_name.

... (continued)

108 of 109 new or added lines in 13 files covered. (99.08%)

4 existing lines in 2 files now uncovered.

1544 of 1671 relevant lines covered (92.4%)

0.92 hits per line

Uncovered Changes

Lines Coverage ∆ File
1
90.24
-2.16% src/peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py

Coverage Regressions

Lines Coverage ∆ File
3
90.24
-2.16% src/peakrdl_busdecoder/cpuif/fanin_intermediate_gen.py
1
99.05
-0.01% src/peakrdl_busdecoder/cpuif/axi4lite/axi4_lite_cpuif.py
Jobs
ID Job ID Ran Files Coverage
1 28897292023.1 07 Jul 2026 08:45PM UTC 36
92.4
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Source Files on build 28897292023
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