nickg / nvc / 28818691952
92%

DEFAULT BRANCH: master
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Jobs 1
Files 103
Run time 9min
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coverage: 92.117% (+0.006%) from 92.111%
28818691952

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nickg 
Implement Verilog disable statements for sequential blocks

Fixes #1605

74 of 76 new or added lines in 2 files covered. (97.37%)

1 existing line in 1 file now uncovered.

79760 of 86586 relevant lines covered (92.12%)

653718.43 hits per line

Uncovered Changes

Lines Coverage ∆ File
2
95.03
 0.02% src/vlog/vlog-lower.c

Coverage Regressions

Lines Coverage ∆ File
1
95.03
 0.02% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 28818691952.1 103
92.12
 GitHub Action Run
Source Files on build 28818691952