nickg / nvc / 28817751394
92%
master: 92%

LAST BUILD BRANCH: issue-1569
DEFAULT BRANCH: master
Ran
Jobs 1
Files 103
Run time 1min
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coverage: 92.114% (+0.003%) from 92.111%
28817751394

push

github

nickg 
Implement Verilog disable statements for sequential blocks

74 of 76 new or added lines in 2 files covered. (97.37%)

1 existing line in 1 file now uncovered.

79758 of 86586 relevant lines covered (92.11%)

646519.09 hits per line

Uncovered Changes

Lines Coverage ∆ File
2
95.03
 0.02% src/vlog/vlog-lower.c

Coverage Regressions

Lines Coverage ∆ File
1
95.03
 0.02% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 28817751394.1 103
92.11
 GitHub Action Run
Source Files on build 28817751394