nickg / nvc / 28699439234
92%
master: 92%

LAST BUILD BRANCH: issue-1569
DEFAULT BRANCH: master
Ran
Jobs 1
Files 104
Run time 1min
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coverage: 92.113% (-0.2%) from 92.286%
28699439234

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github

nickg 
More fixes for Verilog expression width propagation

59 of 60 new or added lines in 2 files covered. (98.33%)

669 existing lines in 12 files now uncovered.

79618 of 86435 relevant lines covered (92.11%)

656712.25 hits per line

Uncovered Changes

Lines Coverage ∆ File
1
95.01
 0.14% src/vlog/vlog-lower.c

Coverage Regressions

Lines Coverage ∆ File
228
66.29
 0.02% src/nvc.c
194
76.54
 -15.67% src/vlog/vlog-number.c
71
95.87
 0.0% src/vlog/vlog-parse.c
51
87.5
 0.12% src/vlog/vlog-dump.c
47
92.18
 -0.88% src/elab.c
28
93.49
 0.19% src/jit/jit-exits.c
16
97.85
 -0.02% src/jit/jit-irgen.c
10
93.13
 0.42% src/vpi/vpi-systf.c
8
93.58
 0.04% src/printf.c
6
95.6
 2.5% src/vlog/vlog-fold.c
6
96.76
 2.5% src/vlog/vlog-simp.c
4
83.23
 0.02% src/vpi/vpi-model.c
Jobs
ID Job ID Ran Files Coverage
1 28699439234.1 104
92.11
 GitHub Action Run
Source Files on build 28699439234