nickg / nvc / 28618288511
92%
master: 92%

LAST BUILD BRANCH: issue-1569
DEFAULT BRANCH: master
Ran
Jobs 1
Files 104
Run time 1min
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Rst
coverage: 92.289% (-0.02%) from 92.305%
28618288511

push

github

nickg 
Handle more Verilog shift corner cases

42 of 46 new or added lines in 3 files covered. (91.3%)

12 existing lines in 3 files now uncovered.

79763 of 86427 relevant lines covered (92.29%)

642099.54 hits per line

Uncovered Changes

Lines Coverage ∆ File
2
94.94
 -0.04% src/vlog/vlog-lower.c
2
84.75
 -0.38% src/vlog/vlog-util.c

Coverage Regressions

Lines Coverage ∆ File
8
92.37
 -0.8% src/vlog/vlog-number.c
3
93.28
 -0.33% src/jit/jit-exits.c
1
97.87
 -0.02% src/jit/jit-irgen.c
Jobs
ID Job ID Ran Files Coverage
1 28618288511.1 104
92.29
 GitHub Action Run
Source Files on build 28618288511