nickg / nvc / 28426875407
92%
master: 92%

LAST BUILD BRANCH: issue-1569
DEFAULT BRANCH: master
Ran
Jobs 1
Files 104
Run time 1min
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coverage: 92.296% (-0.001%) from 92.297%
28426875407

push

github

nickg 
Implement Verilog output and input task ports

46 of 51 new or added lines in 1 file covered. (90.2%)

1 existing line in 1 file now uncovered.

79742 of 86398 relevant lines covered (92.3%)

647676.25 hits per line

Uncovered Changes

Lines Coverage ∆ File
5
94.98
 -0.07% src/vlog/vlog-lower.c

Coverage Regressions

Lines Coverage ∆ File
1
94.98
 -0.07% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 28426875407.1 104
92.3
 GitHub Action Run
Source Files on build 28426875407