nickg / nvc / 27907246078
92%

DEFAULT BRANCH: master
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Jobs 1
Files 104
Run time 1min
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coverage: 92.259% (-0.03%) from 92.284%
27907246078

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nickg 
Add support for default arguments in Verilog macros

Some code and test from @Anselmo95. Closes #1513

79370 of 86030 relevant lines covered (92.26%)

641270.72 hits per line

Coverage Regressions

Lines Coverage ∆ File
79
80.51
 -2.82% src/vhdl/vhdl-lower.c
46
97.14
 0.0% src/lower.c
34
97.78
 0.01% src/mir/mir-node.c
5
95.06
 0.32% src/mir/mir-optim.c
Jobs
ID Job ID Ran Files Coverage
1 27907246078.1 104
92.26
 GitHub Action Run
Source Files on build 27907246078