27719808962
92%
master: 92%

Ran 17 Jun 2026 09:19PM UTC

Jobs 1

Files 104

Run time 1min

Badge

Committed 17 Jun 2026 09:06PM UTC coverage: 92.289% (+0.003%) from 92.286%

Build Type

push

github

Committed by

Commit Message

Rewrite Verilog wait statements with a loop

Coverage Stats

27 of 27 new or added lines in 1 file covered. (100.0%)

26 existing lines in 1 file now uncovered.

79202 of 85820 relevant lines covered (92.29%)

650326.46 hits per line

Lines	Coverage	∆	File
26	93.13	0.0%	src/elab.c

ID	Job ID	Ran	Files	Coverage
1	27719808962.1	17 Jun 2026 09:19PM UTC	104	92.29	GitHub Action Run