nickg / nvc / 26441552539
92%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 104
Run time 1min
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Rst
coverage: 92.273% (+0.004%) from 92.269%
26441552539

push

github

nickg 
cLowering for System Verilog $bits

12 of 13 new or added lines in 1 file covered. (92.31%)

24 existing lines in 2 files now uncovered.

78917 of 85526 relevant lines covered (92.27%)

640585.81 hits per line

Uncovered Changes

Lines Coverage ∆ File
1
93.59
 -0.01% src/vlog/vlog-lower.c

Coverage Regressions

Lines Coverage ∆ File
22
95.56
 0.0% src/lexer.l
2
88.71
 -0.41% src/hash.c
Jobs
ID Job ID Ran Files Coverage
1 26441552539.1 104
92.27
 GitHub Action Run
Source Files on build 26441552539