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fix(mining): correct DPORT SHA hash byte-order to match SW/AHB paths (#428)

DPORT SHA peripheral registers are laid out in REVERSE canonical order:
SHA_TEXT[7] = canonical H[0] (MSB word), SHA_TEXT[0] = canonical H[7] (LSB).
The prior dport_read_digest_swap_if and sha256_hw_dport_kernel read state[]
in register order (state[0]=reg0=canonical LSB), so mining_hash_from_state
placed the canonical LSB bytes at hash_out[0..3]. meets_target reads from
hash[31] down (LE convention, MSB at [31]), so it saw the canonical LSB word
bytes at the most-significant end — producing ~5977 false-positive
record_block calls in minutes on esp32-wroom32 (best_diff stuck at ~1.73).

fix: in both dport_read_digest_swap_if and sha256_hw_dport_kernel step 11,
reverse the register-to-state[] mapping: state[0]=reg7 (canonical MSB)
... state[7]=reg0 (canonical LSB). mining_hash_from_state now writes the
canonical MSB word at hash_out[0..3] — matching SW and AHB LE-internal
byte order that meets_target expects.

early-reject reads SHA_TEXT[7] which IS the canonical MSB register — correct
as-is; no change needed there.

bitaxe-650 (ASIC) and tdongle-s3 (AHB) do not use the DPORT path and are
unaffected; all three boards rebuild clean.

bump BB_POOL_STATS_SCHEMA_VERSION 1→2: force NVS wipe on first boot of this
firmware so esp32's inflated lifetime_blocks (5977 false-positives from the
bug) are cleared. schema sentinel tests updated to inject/expect v2.

fixture tests (block 100,000 known hash) cherry-picked from jae/tm-net-target-debug
to confirm share_meets_network_target expects LE byte order.

Co-authored-by: Claude Sonnet 4.6 <noreply@anthropic.com>

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