nickg / nvc / 26276308025
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 103
Run time 1min
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Rst
coverage: 92.265% (+0.02%) from 92.245%
26276308025

push

github

nickg 
Handle Verilog divison/mod corner cases

7 of 9 new or added lines in 2 files covered. (77.78%)

153 existing lines in 4 files now uncovered.

78711 of 85310 relevant lines covered (92.26%)

649395.47 hits per line

Uncovered Changes

Lines Coverage ∆ File
2
92.77
 0.85% src/vlog/vlog-number.c

Coverage Regressions

Lines Coverage ∆ File
52
82.36
 0.18% src/vpi/vpi-model.c
46
93.51
 0.15% src/vlog/vlog-lower.c
43
91.51
 0.38% src/vpi/vpi-systf.c
12
96.76
 0.08% src/vlog/vlog-sem.c
Jobs
ID Job ID Ran Files Coverage
1 26276308025.1 103
92.26
 GitHub Action Run
Source Files on build 26276308025