24927232832
92%
master: 92%

Ran 25 Apr 2026 09:07AM UTC

Jobs 1

Files 103

Run time 1min

Badge

Committed 25 Apr 2026 08:55AM UTC coverage: 92.197% (-0.009%) from 92.206%

Build Type

push

github

Committed by

Commit Message

Avoid division by zero when simplifying Verilog expression

Coverage Stats

2 of 2 new or added lines in 1 file covered. (100.0%)

32 existing lines in 4 files now uncovered.

77117 of 83644 relevant lines covered (92.2%)

608219.58 hits per line

Lines	Coverage	∆	File
23	87.98	-3.42%	src/vpi/vpi-systf.c
4	69.23	2.2%	src/vpi/vpi-util.c
3	92.33	0.0%	src/printf.c
2	91.65	0.0%	src/vlog/vlog-simp.c

ID	Job ID	Ran	Files	Coverage
1	24927232832.1	25 Apr 2026 09:07AM UTC	103	92.2	GitHub Action Run