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nickg / nvc / 24689573443
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 20 Apr 2026 08:59PM UTC
Jobs 1
Files 102
Run time 1min
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20 Apr 2026 08:47PM UTC coverage: 92.358% (+0.002%) from 92.356%
24689573443

Pull #1513

github

web-flow
Merge 4485415d7 into d88f5611a
Pull Request #1513: Verilog: Support default values on macro functions

6 of 6 new or added lines in 1 file covered. (100.0%)

76778 of 83131 relevant lines covered (92.36%)

602811.77 hits per line

Jobs
ID Job ID Ran Files Coverage
1 24689573443.1 20 Apr 2026 08:59PM UTC 102
92.36
GitHub Action Run
Source Files on build 24689573443
  • Tree
  • List 102
  • Changed 2
  • Source Changed 0
  • Coverage Changed 2
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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  • Pull Request #1513
  • PR Base - master (#24634463149)
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