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nickg / nvc / 24502255087
92%

Build:
DEFAULT BRANCH: master
Ran 16 Apr 2026 09:28AM UTC
Jobs 1
Files 102
Run time 1min
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16 Apr 2026 08:56AM UTC coverage: 92.339% (+0.004%) from 92.335%
24502255087

push

github

nickg
Fix lowering of Verilog repeat with non-constant count

4 of 4 new or added lines in 1 file covered. (100.0%)

193 existing lines in 6 files now uncovered.

76689 of 83052 relevant lines covered (92.34%)

609111.83 hits per line

Coverage Regressions

Lines Coverage ∆ File
78
93.76
0.01% src/vlog/vlog-lower.c
63
82.29
0.05% src/vpi/vpi-model.c
25
93.55
0.08% src/jit/jit-exits.c
19
97.74
0.01% src/jit/jit-irgen.c
7
97.78
0.0% src/mir/mir-node.c
1
88.3
-0.14% src/jit/jit-interp.c
Jobs
ID Job ID Ran Files Coverage
1 24502255087.1 16 Apr 2026 09:28AM UTC 102
92.34
GitHub Action Run
Source Files on build 24502255087
  • Tree
  • List 102
  • Changed 8
  • Source Changed 0
  • Coverage Changed 8
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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