nickg / nvc / 24303565816
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 102
Run time 1min
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Rst
coverage: 92.333% (-0.003%) from 92.336%
24303565816

Pull #1491

github

web-flow 
Merge 8978194b7 into 978a1a7bd
Pull Request #1491: Verilog: allow trailing // comments on `define lines

146 of 158 new or added lines in 7 files covered. (92.41%)

3 existing lines in 2 files now uncovered.

76577 of 82936 relevant lines covered (92.33%)

616505.32 hits per line

Uncovered Changes

Lines Coverage ∆ File
12
78.13
 4.34% src/vhdl/vhdl-lower.c

Coverage Regressions

Lines Coverage ∆ File
2
78.13
 4.34% src/vhdl/vhdl-lower.c
1
88.3
 -0.14% src/jit/jit-interp.c
Jobs
ID Job ID Ran Files Coverage
1 24303565816.1 102
92.33
 GitHub Action Run
Source Files on build 24303565816