nickg / nvc / 24148831966

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Commit Message

Verilog: support generate case and else-if constructs (#1484)

Add parsing support for two generate constructs that were previously
unsupported:

1. case generate construct (IEEE 1800-2023 section 27.5):
   Parses case/endcase in generate context and lowers it to an
   equivalent V_IF_GENERATE with equality comparisons, so the
   existing simplifier and elaborator handle it without a new node
   kind.  Supports multiple comma-separated labels per alternative
   and the default branch.

2. else-if in if generate construct:
   Previously only a single else branch was parsed.  Now chains of
   else-if are collected as additional V_COND entries in the same
   V_IF_GENERATE node, matching the existing simplifier logic that
   iterates over multiple conditions.

Both constructs are commonly used in Xilinx Vivado-generated IP
cores (e.g. gtwizard_ultrascale GT transceiver wrappers).

Co-authored-by: Rafał Hibner <rafal.hibner@secom.com.pl>

Coverage Stats

43 of 50 new or added lines in 1 file covered. (86.0%)

1 existing line in 1 file now uncovered.

76267 of 82533 relevant lines covered (92.41%)

594992.75 hits per line