nickg / nvc / 23150555036
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 102
Run time 1min
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Rst
coverage: 92.475% (-0.007%) from 92.482%
23150555036

Pull #1447

github

web-flow 
Merge d86bebf16 into a7623c165
Pull Request #1447: Adding VHDL-2019 range records.

108 of 122 new or added lines in 5 files covered. (88.52%)

1 existing line in 1 file now uncovered.

77899 of 84238 relevant lines covered (92.47%)

436809.05 hits per line

Uncovered Changes

Lines Coverage ∆ File
7
96.34
 -0.06% src/parse.c
5
95.75
 -0.13% src/names.c
2
96.98
 -0.05% src/sem.c

Coverage Regressions

Lines Coverage ∆ File
1
88.3
 -0.14% src/jit/jit-interp.c
Jobs
ID Job ID Ran Files Coverage
1 23150555036.1 102
92.47
 GitHub Action Run
Source Files on build 23150555036