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nickg / nvc / 22217050364
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 20 Feb 2026 08:41AM UTC
Jobs 1
Files 102
Run time 1min
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20 Feb 2026 08:31AM UTC coverage: 92.602%. Remained the same
22217050364

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nickg
Handle Verilog ports with initial value

19 of 19 new or added lines in 2 files covered. (100.0%)

2 existing lines in 1 file now uncovered.

76814 of 82951 relevant lines covered (92.6%)

442954.48 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
2
88.71
-0.41% src/hash.c
Jobs
ID Job ID Ran Files Coverage
1 22217050364.1 20 Feb 2026 08:41AM UTC 102
92.6
GitHub Action Run
Source Files on build 22217050364
  • Tree
  • List 102
  • Changed 4
  • Source Changed 0
  • Coverage Changed 4
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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