nickg / nvc / 21783896992
93%
master: 93%

LAST BUILD BRANCH: v1.19-branch
DEFAULT BRANCH: master
Ran
Jobs 1
Files 102
Run time 1min
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Rst
coverage: 92.599% (-0.006%) from 92.605%
21783896992

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github

nickg 
Refactor copying in VHDL instantiation

68 of 72 new or added lines in 7 files covered. (94.44%)

4 existing lines in 3 files now uncovered.

76625 of 82749 relevant lines covered (92.6%)

435853.77 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
98.75
 -0.13% src/inst.c
3
61.68
 -0.1% src/dump.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
98.75
 -0.13% src/inst.c
1
88.43
 -0.14% src/jit/jit-interp.c
2
97.17
 -0.03% src/lower.c
Jobs
ID Job ID Ran Files Coverage
1 21783896992.1 102
92.6
 GitHub Action Run
Source Files on build 21783896992