nickg / nvc / 19747205009
93%
master: 93%

LAST BUILD BRANCH: coverage-cleanups
DEFAULT BRANCH: master
Ran
Jobs 1
Files 100
Run time 1min
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Rst
coverage: 92.555% (-0.01%) from 92.565%
19747205009

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github

nickg 
Handle unary operations on Verilog reals

22 of 27 new or added lines in 1 file covered. (81.48%)

226 existing lines in 4 files now uncovered.

75233 of 81285 relevant lines covered (92.55%)

454692.52 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
5
94.14
 -0.07% src/vlog/vlog-lower.c

Uncovered Existing Lines

Lines Coverage ∆ File
22
88.57
 0.0% src/scan.c
23
95.29
 -0.2% src/lexer.l
53
94.14
 -0.07% src/vlog/vlog-lower.c
128
95.99
 -0.22% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 19747205009.1 100
92.55
 GitHub Action Run
Source Files on build 19747205009