nickg / nvc / 18761175291
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 100
Run time 1min
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Rst
coverage: 92.574% (+0.006%) from 92.568%
18761175291

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github

nickg 
Handle Verilog strings in trans_expr

12 of 12 new or added lines in 1 file covered. (100.0%)

78 existing lines in 2 files now uncovered.

74810 of 80811 relevant lines covered (92.57%)

461265.67 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
1
76.47
 1.25% src/vlog/vlog-trans.c
77
97.19
 0.0% src/sem.c
Jobs
ID Job ID Ran Files Coverage
1 18761175291.1 100
92.57
 GitHub Action Run
Source Files on build 18761175291