nickg / nvc / 18248879785
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 100
Run time 1min
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Rst
coverage: 92.739% (+0.02%) from 92.716%
18248879785

push

github

nickg 
Improve type checking for Verilog binary operators

21 of 22 new or added lines in 1 file covered. (95.45%)

197 existing lines in 6 files now uncovered.

74753 of 80606 relevant lines covered (92.74%)

570051.28 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
94.18
 0.81% src/vlog/vlog-sem.c

Uncovered Existing Lines

Lines Coverage ∆ File
10
94.92
 0.0% src/vlog/vlog-lower.c
10
95.07
 0.0% src/vlog/vlog-node.c
13
94.18
 0.81% src/vlog/vlog-sem.c
20
95.49
 0.36% src/lexer.l
22
88.57
 0.0% src/scan.c
122
96.23
 0.11% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 18248879785.1 100
92.74
 GitHub Action Run
Source Files on build 18248879785