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nickg / nvc / 18079196157
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 28 Sep 2025 08:20PM UTC
Jobs 1
Files 100
Run time 1min
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28 Sep 2025 08:06PM UTC coverage: 92.65% (-0.01%) from 92.662%
18079196157

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nickg
Run Verilog and VHDL processes concurrently

39 of 39 new or added lines in 3 files covered. (100.0%)

411 existing lines in 11 files now uncovered.

74140 of 80022 relevant lines covered (92.65%)

582366.52 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
8
95.07
0.0% src/vlog/vlog-node.c
8
91.37
0.19% src/vpi/vpi-systf.c
9
97.25
-0.11% src/mir/mir-node.c
13
85.04
-0.06% src/jit/jit-ffi.c
14
88.64
-0.13% src/vlog/vlog-udp.c
25
94.57
0.13% src/jit/jit-exits.c
35
97.56
0.02% src/jit/jit-irgen.c
38
92.11
1.14% src/vlog/vlog-number.c
41
94.84
-1.2% src/vlog/vlog-lower.c
110
94.23
0.05% src/rt/model.c
110
96.07
-0.13% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 18079196157.1 28 Sep 2025 08:20PM UTC 100
92.65
GitHub Action Run
Source Files on build 18079196157
  • Tree
  • List 100
  • Changed 12
  • Source Changed 0
  • Coverage Changed 12
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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