nickg / nvc / 17927321823
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 100
Run time 1min
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Rst
coverage: 92.658% (+0.02%) from 92.641%
17927321823

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github

nickg 
Add Verilog remainder and division operators

9 of 10 new or added lines in 2 files covered. (90.0%)

115 existing lines in 4 files now uncovered.

73865 of 79718 relevant lines covered (92.66%)

572397.89 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
96.05
 -0.08% src/vlog/vlog-lower.c

Uncovered Existing Lines

Lines Coverage ∆ File
2
98.95
 -0.52% src/cov/cov-report.c
11
98.3
 0.4% src/cov/cov-html.c
18
74.11
 1.22% src/util.c
84
65.35
 0.17% src/nvc.c
Jobs
ID Job ID Ran Files Coverage
1 17927321823.1 100
92.66
 GitHub Action Run
Source Files on build 17927321823