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nickg / nvc / 17726179213
93%

Build:
DEFAULT BRANCH: master
Ran 15 Sep 2025 08:12AM UTC
Jobs 1
Files 99
Run time 1min
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15 Sep 2025 07:41AM UTC coverage: 92.613% (+0.006%) from 92.607%
17726179213

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github

nickg
Schedule Verilog zero delays in inactive region

44 of 44 new or added lines in 2 files covered. (100.0%)

407 existing lines in 10 files now uncovered.

73694 of 79572 relevant lines covered (92.61%)

575822.84 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
9
95.07
-4.04% src/vlog/vlog-node.c
10
97.36
0.01% src/mir/mir-node.c
16
97.0
0.01% src/mir/mir-vcode.c
18
96.37
0.02% src/vlog/vlog-lower.c
21
94.44
0.08% src/jit/jit-exits.c
32
97.52
0.02% src/jit/jit-irgen.c
53
96.79
0.0% src/vcode.c
58
94.86
0.0% src/elab.c
85
97.25
0.0% src/lower.c
105
94.19
0.13% src/rt/model.c
Jobs
ID Job ID Ran Files Coverage
1 17726179213.1 15 Sep 2025 08:12AM UTC 99
92.61
GitHub Action Run
Source Files on build 17726179213
  • Tree
  • List 99
  • Changed 12
  • Source Changed 0
  • Coverage Changed 12
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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