nickg / nvc / 17528137955
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 1min
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Rst
coverage: 92.611% (-0.02%) from 92.634%
17528137955

push

github

nickg 
Improve handling of escape sequences in Verilog strings

43 of 70 new or added lines in 5 files covered. (61.43%)

100 existing lines in 4 files now uncovered.

73450 of 79310 relevant lines covered (92.61%)

574877.48 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
89.3
 -0.09% src/vlog/vlog-dump.c
26
91.42
 -2.06% src/lexer.l

Uncovered Existing Lines

Lines Coverage ∆ File
1
89.64
 -0.16% src/diag.c
1
88.79
 0.03% src/scan.c
11
91.42
 -2.06% src/lexer.l
87
96.19
 -0.01% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 17528137955.1 99
92.61
 GitHub Action Run
Source Files on build 17528137955