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nickg / nvc / 17501976036
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran 05 Sep 2025 07:08PM UTC
Jobs 1
Files 99
Run time 1min
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05 Sep 2025 06:47PM UTC coverage: 92.627% (+0.008%) from 92.619%
17501976036

push

github

nickg
Lower arrays of Verilog wires

17 of 17 new or added lines in 1 file covered. (100.0%)

227 existing lines in 6 files now uncovered.

73108 of 78927 relevant lines covered (92.63%)

586090.05 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
3
97.34
0.0% src/mir/mir-node.c
5
95.52
-0.33% src/vlog/vlog-simp.c
16
75.47
3.1% src/vlog/vlog-trans.c
53
96.44
0.05% src/vlog/vlog-lower.c
70
97.44
0.16% src/jit/jit-irgen.c
80
96.41
0.0% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 17501976036.1 05 Sep 2025 07:08PM UTC 99
92.63
GitHub Action Run
Source Files on build 17501976036
  • Tree
  • List 99
  • Changed 6
  • Source Changed 0
  • Coverage Changed 6
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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