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nickg / nvc / 17274398479
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran 27 Aug 2025 05:55PM UTC
Jobs 1
Files 98
Run time 1min
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27 Aug 2025 05:43PM UTC coverage: 92.579% (+0.004%) from 92.575%
17274398479

push

github

nickg
Verilog reduction and/or for wide vectors

54 of 54 new or added lines in 3 files covered. (100.0%)

2 existing lines in 1 file now uncovered.

72566 of 78383 relevant lines covered (92.58%)

551026.95 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
2
94.42
-0.04% src/jit/jit-exits.c
Jobs
ID Job ID Ran Files Coverage
1 17274398479.1 27 Aug 2025 05:55PM UTC 98
92.58
GitHub Action Run
Source Files on build 17274398479
  • Tree
  • List 98
  • Changed 3
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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