pybricks / pybricks-micropython / 16753503016
56%

DEFAULT BRANCH: master
Ran
Jobs 2
Files 122
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 56.973%. Remained the same
16753503016

push

github

ArcaneNibble 
pbio/drv: Handle cache ops for EV3 drivers

This allows the main memory to be write-back cached.

Special note regarding DMA buffers and the uncached alias mapping:
DMA buffers and uncached data cannot safely share cache lines
with unrelated data! We use a special macro to align these buffers
so that issues do not occur.

If DMA RX buffers share cache lines with other data, it can lead to
race conditions which corrupt data. If we flush and invalidate
the cache before performing the DMA, reading the unrelated data
can cause the cache line to be loaded back into cache, cancelling
out the invalidation. If we wait until after performing the DMA
and perform a flush and invalidate, the flush can corrupt part of
the data which was written by the DMA. If we only perform an invalidate,
writes to the unrelated data can be lost.

A similar race condition can happen if an uncached alias is used
to read/write to data which sits next to unrelated data.
This currently applies to the ADC RX buffer.

The USB driver's CPPI descriptors are safe as they happen to already
be cache line aligned.

The solution we use here is to place each buffer in its own
cache-line-aligned block of memory and only perform an invalidate
upon DMA completion. This makes sure that no unrelated data can
get caught up in the same cache lines.

This issue does not affect DMA TX buffers written using the
normal cached mapping. Those are handled by flushing the cache.

3885 of 6819 relevant lines covered (56.97%)

20666062.59 hits per line

Jobs
ID Job ID Ran Files Coverage
1 PBIO - 16753503016.1 72
60.99
 GitHub Action Run
2 virtualhub - 16753503016.2 94
50.07
 GitHub Action Run
Source Files on build 16753503016