• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

nickg / nvc / 16328150857
93%

Build:
DEFAULT BRANCH: master
Ran 16 Jul 2025 07:21PM UTC
Jobs 1
Files 99
Run time 2min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

16 Jul 2025 07:09PM UTC coverage: 92.439% (+0.02%) from 92.424%
16328150857

push

github

nickg
Dump Verilog types in FST waveform

Issue #1227

47 of 47 new or added lines in 4 files covered. (100.0%)

1 existing line in 1 file now uncovered.

71731 of 77598 relevant lines covered (92.44%)

554041.15 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
1
97.3
0.0% src/jit/jit-irgen.c
Jobs
ID Job ID Ran Files Coverage
1 16328150857.1 16 Jul 2025 07:21PM UTC 99
92.44
GitHub Action Run
Source Files on build 16328150857
  • Tree
  • List 99
  • Changed 5
  • Source Changed 0
  • Coverage Changed 5
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • b082ba4f on github
  • Prev Build on master (#16327765883)
  • Next Build on master (#16364622566)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc