nickg / nvc / 16178773610
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.379% (+0.03%) from 92.346%
16178773610

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github

nickg 
Intern Verilog numbers

71 of 77 new or added lines in 2 files covered. (92.21%)

215 existing lines in 10 files now uncovered.

71567 of 77471 relevant lines covered (92.38%)

564268.18 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
6
88.55
 8.25% src/vlog/vlog-number.c

Uncovered Existing Lines

Lines Coverage ∆ File
6
95.86
 0.16% src/vlog/vlog-sem.c
13
94.9
 0.02% src/elab.c
14
88.55
 8.25% src/vlog/vlog-number.c
15
95.25
 0.06% src/common.c
15
97.29
 -0.09% src/jit/jit-irgen.c
17
88.41
 3.88% src/vlog/vlog-simp.c
24
96.98
 -0.05% src/vlog/vlog-lower.c
30
85.61
 0.03% src/vpi/vpi-model.c
31
89.15
 0.02% src/vlog/vlog-dump.c
50
94.07
 0.01% src/rt/model.c
Jobs
ID Job ID Ran Files Coverage
1 16178773610.1 98
92.38
 GitHub Action Run
Source Files on build 16178773610