nickg / nvc / 16178543600
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.379% (+0.02%) from 92.356%
16178543600

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github

nickg 
Intern Verilog numbers

71 of 77 new or added lines in 2 files covered. (92.21%)

34 existing lines in 5 files now uncovered.

71567 of 77471 relevant lines covered (92.38%)

566934.55 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
6
88.55
 8.25% src/vlog/vlog-number.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
96.98
 -0.09% src/vlog/vlog-lower.c
3
97.29
 -0.1% src/jit/jit-irgen.c
3
88.41
 1.67% src/vlog/vlog-simp.c
13
94.9
 0.02% src/elab.c
14
88.55
 8.25% src/vlog/vlog-number.c
Jobs
ID Job ID Ran Files Coverage
1 16178543600.1 98
92.38
 GitHub Action Run
Source Files on build 16178543600