• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

nickg / nvc / 16080534785
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 04 Jul 2025 08:40PM UTC
Jobs 1
Files 98
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

04 Jul 2025 08:28PM UTC coverage: 92.284% (-0.003%) from 92.287%
16080534785

push

github

nickg
Parse Verilog genvar declarations

75 of 75 new or added lines in 3 files covered. (100.0%)

11 existing lines in 4 files now uncovered.

70915 of 76844 relevant lines covered (92.28%)

567705.88 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
1
88.82
-0.15% src/jit/jit-interp.c
2
96.51
0.12% src/vlog/vlog-parse.c
3
90.28
-0.53% src/thread.c
5
89.63
-1.08% src/hash.c
Jobs
ID Job ID Ran Files Coverage
1 16080534785.1 04 Jul 2025 08:39PM UTC 98
92.28
GitHub Action Run
Source Files on build 16080534785
  • Tree
  • List 98
  • Changed 8
  • Source Changed 0
  • Coverage Changed 8
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • 2783b174 on github
  • Prev Build on master (#16068871472)
  • Next Build on test (#16099065297)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc