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nickg / nvc / 16044413472
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 03 Jul 2025 07:48AM UTC
Jobs 1
Files 98
Run time 3min
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03 Jul 2025 07:35AM UTC coverage: 92.258% (-0.007%) from 92.265%
16044413472

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github

nickg
Elaborate Verilog if-generate construct

56 of 76 new or added lines in 5 files covered. (73.68%)

70774 of 76713 relevant lines covered (92.26%)

572897.83 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
3
94.77
-0.2% src/elab.c
3
85.96
2.62% src/vlog/vlog-simp.c
14
84.91
-1.72% src/vlog/vlog-number.c
Jobs
ID Job ID Ran Files Coverage
1 16044413472.1 03 Jul 2025 07:48AM UTC 98
92.26
GitHub Action Run
Source Files on build 16044413472
  • Tree
  • List 98
  • Changed 5
  • Source Changed 0
  • Coverage Changed 5
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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