nickg / nvc / 14572390307
92%
master: 92%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 95
Run time 1min
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Rst
coverage: 92.316% (+0.006%) from 92.31%
14572390307

push

github

nickg 
Add Vec2 and Vec4 types for Verilog vectors

151 of 162 new or added lines in 4 files covered. (93.21%)

5 existing lines in 3 files now uncovered.

69178 of 74936 relevant lines covered (92.32%)

419480.12 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
96.75
 -0.15% src/mir/mir-node.c
7
97.65
 -0.19% src/jit/jit-irgen.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
83.91
 0.5% src/mir/mir-type.c
1
90.11
 -0.18% src/thread.c
3
97.65
 -0.19% src/jit/jit-irgen.c
Jobs
ID Job ID Ran Files Coverage
1 14572390307.1 95
92.32
 GitHub Action Run
Source Files on build 14572390307