nickg / nvc / 12557883011
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 86
Run time 1min
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coverage: 92.059% (+0.04%) from 92.023%
12557883011

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github

nickg 
Define Verilog preprocessor macros on command line

59 of 65 new or added lines in 7 files covered. (90.77%)

1 existing line in 1 file now uncovered.

63695 of 69189 relevant lines covered (92.06%)

517323.47 hits per line

Jobs
ID Job ID Ran Files Coverage
1 12557883011.1 0
92.06
 GitHub Action Run
Source Files on build 12557883011
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