nickg / nvc / 12215712200
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 84
Run time 1min
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Rst
coverage: 91.968% (+0.001%) from 91.967%
12215712200

push

github

nickg 
Handle expression in Verilog net declarations

44 of 45 new or added lines in 3 files covered. (97.78%)

120 existing lines in 4 files now uncovered.

63122 of 68635 relevant lines covered (91.97%)

627648.81 hits per line

Jobs
ID Job ID Ran Files Coverage
1 12215712200.1 0
91.97
 GitHub Action Run
Source Files on build 12215712200
Detailed source file information is not available for this build.