• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

nickg / nvc / 12215712200
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: fuzz/4f9dd1c
DEFAULT BRANCH: master
Ran 07 Dec 2024 08:12PM UTC
Jobs 1
Files 84
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

07 Dec 2024 08:02PM UTC coverage: 91.968% (+0.001%) from 91.967%
12215712200

push

github

nickg
Handle expression in Verilog net declarations

44 of 45 new or added lines in 3 files covered. (97.78%)

120 existing lines in 4 files now uncovered.

63122 of 68635 relevant lines covered (91.97%)

627648.81 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
91.24
0.06% src/vlog/vlog-parse.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
90.16
-0.18% src/thread.c
23
91.97
0.05% src/lexer.l
34
92.74
-0.09% src/vlog/vlog-lower.c
62
91.24
0.06% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 12215712200.1 07 Dec 2024 08:12PM UTC 84
91.97
GitHub Action Run
Source Files on build 12215712200
  • Tree
  • List 84
  • Changed 57
  • Source Changed 0
  • Coverage Changed 5
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • d92bb321 on github
  • Prev Build on test (#12178843586)
  • Next Build on test (#12215868040)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc