nickg / nvc / 12215712200
93%
master: 93%

LAST BUILD BRANCH: fuzz/4f9dd1c
DEFAULT BRANCH: master
Ran
Jobs 1
Files 84
Run time 1min
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Rst
coverage: 91.968% (+0.001%) from 91.967%
12215712200

push

github

nickg 
Handle expression in Verilog net declarations

44 of 45 new or added lines in 3 files covered. (97.78%)

120 existing lines in 4 files now uncovered.

63122 of 68635 relevant lines covered (91.97%)

627648.81 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
91.24
 0.06% src/vlog/vlog-parse.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
90.16
 -0.18% src/thread.c
23
91.97
 0.05% src/lexer.l
34
92.74
 -0.09% src/vlog/vlog-lower.c
62
91.24
 0.06% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 12215712200.1 84
91.97
 GitHub Action Run
Source Files on build 12215712200