nickg / nvc / 9571824330
93%

DEFAULT BRANCH: master
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Jobs 1
Files 79
Run time 1min
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coverage: 91.563% (+0.01%) from 91.553%
9571824330

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github

nickg 
Fix parsing of non-ANSI Verilog port declarations. Issue 811

56788 of 62021 relevant lines covered (91.56%)

663660.82 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
1
89.05
 -0.18% src/thread.c
Jobs
ID Job ID Ran Files Coverage
1 9571824330.1 79
91.56
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Source Files on build 9571824330