nickg / nvc / 9521094365
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 79
Run time 7min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 91.55% (-0.005%) from 91.555%
9521094365

push

github

nickg 
Implement `ifdef, `ifndef, etc. in Verilog preprocessor

56 of 57 new or added lines in 1 file covered. (98.25%)

8 existing lines in 2 files now uncovered.

56771 of 62011 relevant lines covered (91.55%)

662420.78 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
97.66
 1.82% src/vlog/vlog-pp.l

Uncovered Existing Lines

Lines Coverage ∆ File
1
89.05
 -0.18% src/thread.c
7
75.21
 -1.19% src/server.c
Jobs
ID Job ID Ran Files Coverage
1 9521094365.1 79
91.55
 GitHub Action Run
Source Files on build 9521094365