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nickg / nvc / 9521094365
93%

Build:
DEFAULT BRANCH: master
Ran 14 Jun 2024 07:14PM UTC
Jobs 1
Files 79
Run time 7min
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14 Jun 2024 06:45PM UTC coverage: 91.55% (-0.005%) from 91.555%
9521094365

push

github

nickg
Implement `ifdef, `ifndef, etc. in Verilog preprocessor

56 of 57 new or added lines in 1 file covered. (98.25%)

8 existing lines in 2 files now uncovered.

56771 of 62011 relevant lines covered (91.55%)

662420.78 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
97.66
1.82% src/vlog/vlog-pp.l

Uncovered Existing Lines

Lines Coverage ∆ File
1
89.05
-0.18% src/thread.c
7
75.21
-1.19% src/server.c
Jobs
ID Job ID Ran Files Coverage
1 9521094365.1 14 Jun 2024 07:14PM UTC 79
91.55
GitHub Action Run
Source Files on build 9521094365
  • Tree
  • List 79
  • Changed 27
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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