nickg / nvc / 9520918318
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 79
Run time 1min
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coverage: 91.55% (-0.005%) from 91.555%
9520918318

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github

nickg 
Implement `ifdef, `ifndef, etc. in Verilog preprocessor

56 of 57 new or added lines in 1 file covered. (98.25%)

8 existing lines in 2 files now uncovered.

56771 of 62011 relevant lines covered (91.55%)

660777.94 hits per line

Jobs
ID Job ID Ran Files Coverage
1 9520918318.1 0
91.55
 GitHub Action Run
Source Files on build 9520918318
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