perf-toolbox / tir / 8869177395
88%

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Jobs 1
Files 18
Run time 1min
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coverage: 80.135% (+0.2%) from 79.965%
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refactor: better handling of RISC-V registers (#33)

It turns out that RISC-V registers are much more complicated than the initial design was prepared for. Re-think how to describe all the registers in a DSL.

21 of 36 new or added lines in 2 files covered. (58.33%)

476 of 594 relevant lines covered (80.13%)

6.88 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
3
70.87
 0.0% backends/riscv/src/ops/alu.rs
12
65.71
 15.71% backends/riscv/src/registers.rs
Jobs
ID Job ID Ran Files Coverage
1 8869177395.1 18
80.13
 GitHub Action Run
Source Files on build 8869177395