StanfordAHA / garnet / 1573
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Genesis/Verilog Fixes (#157)

* Change global controller dependencies to .svp to make DC happy

* Fix read_data error in test_lut

* Ensure that the read_data output from test_lut is always defined

2208 of 2319 relevant lines covered (95.21%)

0.95 hits per line

Jobs
ID Job ID Ran Files Coverage
1 1573.1 0
95.21
 Travis Job 1573.1
Source Files on build 1573
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