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chiranthsiddappa / caf_verilog / 47
86%
master: 90%

Build:
Build:
LAST BUILD BRANCH: prepend-keys
DEFAULT BRANCH: master
Ran 17 Nov 2018 06:19PM UTC
Jobs 3
Files 14
Run time 1min
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Chiranth Siddappa
Merge branch 'master' into dot-prod-pip

293 of 391 relevant lines covered (74.94%)

1.5 hits per line

Jobs
ID Job ID Ran Files Coverage
1 47.1 17 Nov 2018 06:21PM UTC 0
0.26
Travis Job 47.1
2 47.2 17 Nov 2018 06:19PM UTC 0
74.94
Travis Job 47.2
3 47.3 17 Nov 2018 06:20PM UTC 0
74.94
Travis Job 47.3
Source Files on build 47
  • List 0
  • Changed 0
  • Source Changed 0
  • Coverage Changed 0
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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  • Build #47
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