chiranthsiddappa / caf_verilog / 155

Builds Branch Commit Type Ran Committer Via Coverage
155 caf almost getting all values out of caf; cpx_multiply needs original bit selection push Chiranth Siddappa travis-ci-com pending completion   set done
154 caf Removing pipeline register since it's unused now push Chiranth Siddappa travis-ci-com pending completion   set done
153 caf Adding caf wiring changes for yi and yq push Chiranth Siddappa travis-ci-com pending completion   set done
152 caf Final changes to make sure handshake deasserts valid and resets the index push Chiranth Siddappa travis-ci-com pending completion   set done
151 caf tb changes as caf module was being worked on push Chiranth Siddappa travis-ci-com pending completion   set done
149 caf Sig Gen responds with result on first handshake push Chiranth Siddappa travis-ci-com pending completion   set done
148 caf Adding new state for setting shifts and phase increments push Chiranth Siddappa travis-ci-com pending completion   set done
147 caf Removing blank cell from the end of the file push Chiranth Siddappa travis-ci-com pending completion   set done
146 caf Changes added to better handle delay and proper axi compliance push Chiranth Siddappa travis-ci-com pending completion   set done
145 caf Adding changes to use fs and n bits for the caf push Chiranth Siddappa travis-ci-com pending completion   set done
144 caf Moving binary writer to the io helper module push Chiranth Siddappa travis-ci-com pending completion   set done
143 caf Making changes to write output the testbench push Chiranth Siddappa travis-ci-com pending completion   set done
142 caf Able to write reference and capture buffers and wire them into the caf module push Chiranth Siddappa travis-ci-com pending completion   set done
141 caf Adding signal changes for capture buffer push Chiranth Siddappa travis-ci-com pending completion   set done
140 caf Manual merge; missing arg_max_inst.v push Chiranth Siddappa travis-ci-com pending completion   set done