leonardt / silica / 358

Builds Branch Commit Type Ran Committer Via Coverage
358 master Add missing .py file push leonardt travis-ci pending completion   set done
357 uart-shift Add missing .py file push leonardt travis-ci pending completion   set done
352 master Minor changes to JTAG and FIFO push leonardt travis-ci pending completion   set done
351 master Serializer using mem push leonardt travis-ci pending completion   set done
350 master Refactor lbmem example into multiple coroutines push leonardt travis-ci pending completion   set done
344 master Merge pull request #18 from leonardt/verilog_fix Verilog fix push web-flow travis-ci pending completion   set done
337 verilog_fix couple of minor fixes. send_cnt was not being initialized in one of them Pull #18 web-flow travis-ci pending completion   set done
336 verilog_fix couple of minor fixes. send_cnt was not being initialized in one of them push rdaly525 travis-ci pending completion   set done
335 verilog_fix cleaned up verilog to explicitly indicate constant bitwidths. used single bit when adding 1. push rdaly525 travis-ci pending completion   set done
334 xmodem Update all tests to annotate outputs push leonardt travis-ci pending completion   set done
332 master Update evaluation notebook push leonardt travis-ci pending completion   set done
329 tap Add import Pull #16 web-flow travis-ci pending completion   set done
328 tap Add import push leonardt travis-ci pending completion   set done
323 tap Add clock frequency graph Pull #16 web-flow travis-ci pending completion   set done
322 tap Add clock frequency graph push leonardt travis-ci pending completion   set done